As integrated circuits, such as very large scale integration (VIS) circuits increase in complexity, operating speed, and power consumption, the ability to test such circuits becomes more difficult. Analog circuits, in particular, are formed using ultra-deep sub micron process technologies, and such circuits often exhibit behavior unobservable through circuit simulations. It is, therefore, desirable to be able to measure on-chip analog voltages during testing of such integrated circuits for purposes of verification of the circuit against design simulations.
In order to measure analog voltages present within an integrated circuit, chip or die (it is noted that these terms are used synonymously for an integrated circuit), it is known to bring an on-chip signal off of the chip for measurements. One such arrangement 100 is illustrated in FIG. 1. As shown the arrangement includes a test analog voltage 102, which is located on a chip or die delivered to an I/O pad 104 in order to take the voltage off of the chip for measurement. When the voltage being tested is taken off-chip through the I/O pad 104, the voltage may then be measured with an oscilloscope or multimeter 106. The circuit of FIG. 1 in this way allows open-circuit voltage measurements with the multimeter or oscilloscope 106, which normally is a high impedance device.
When being taken off-chip, however, the voltage must travel from the chip or die via a package 108 in which the chip or die is housed. The package includes bond wires or redistribution layers (RDL, as used in “flip-chip” technology), which introduce parasitic effects, such as parasitic capacitance. Moreover, the analog voltage also will typically be routed via printed circuit board (pcb) traces on a board 110 to which the package 108 is mounted, introducing even more parasitic effects. If, however, the test analog voltage 102 is weak, the integrity of the signal might not be able to withstand the parasitic effects of the I/O pad 104, package 108, and the board 110 leading to an inability to measure the voltage accurately with the multimeter or oscilloscope 106.
In order to overcome the disadvantages of the arrangement of FIG. 1, it is also known to increase drive strengths of weak on-chip analog signals through the use of a driver, such as a buffer. In particular, FIG. 2 illustrates an arrangement 200 having such a buffer 202 that receives the test analog voltage 204 and drives the signal to an I/O pad 206. As an example, the buffer 202 could be realized with an operational amplifier connected in unity gain configuration. From the pad 206, the signal is sent via a package 208 and a printed circuit board trace 210 on which the package 208 is mounted to a multimeter or oscilloscope 212 for measurement. With this arrangement, however, non-ideal effects that affect the accuracy of the test analog voltage 204 off-chip may include an inherent offset voltage of the analog buffer 202, as well as noise and losses that accumulate from the I/O pad 206, the package 208 and the board 210.
Another known arrangement for on-chip voltage measurement may include the use of analog-to-digital converter (ADC) that affords on-chip measurement of the analog voltages. In particular, FIG. 3 illustrates such an arrangement 300 where a test analog voltage 302 is delivered to an ADC 304, which converts the test analog voltage 302 to a digital value of N-bits 308 based on conversion with respect to reference voltage(s) 306. The digital value of N-bits 308 is then sent to a hardware registrar 310 for temporary storage to be read out via a connection 312 to a register interface 314 and then to a logic (not shown) located on the chip. The arrangement of FIG. 3, however, although providing increased testability because the test voltage is not brought off-chip, and mitigating the non-ideal effects picked up through the path of an I/O pad, package, and board, is nonetheless very costly in terms of silicon area. Additionally, such an arrangement 300 adds further complexity that makes this type of testing structure unfeasible for many highly integrated ASIC designs.